Power Factor Correction (PFC) circuits are used to minimize unwanted disturbances in AC power lines, and to provide a constant DC output voltage under all load conditions. The AC line disturbances are caused by normal operation of DC powered electrical equipment, and are exhibited as phase shift of the AC input current and distortion of the current waveform. The PFC minimizes the distortion and corrects the phase shift. Existing PFC control circuits are complex, difficult and time consuming to implement, and have a limited dynamic range. By incorporating a power factor correction circuit between the alternating current supply and the direct current supply connected to the load, however, harmonic distortion in the AC power line is reduced; and the operational characteristics of some electrical equipment is improved. It is desirable to provide an improved PFC control circuit which is simple, has a wide dynamic range and requires minimal expertise to implement using a variable Amplitude Regulator (VAR) to accomplish this by using simple resistive scaling, instead of complex multiply and divide circuit functions, to product the PFC control signal.
It is an object of this invention to provide an improved power factor correction (PFC) system.
It is another object of this invention to provide an improved variable amplitude regulator (VAR) signal interface in a switch-mode PFC system.
It is an additional object of this invention to provide an improved analog variable amplitude voltage regulator for use in a power factor correction system.
It is a further object of this invention to provide an improved variable amplitude voltage regulator (VAR) for use in a power factor correction system in which the VAR interface functions as a resistor scaling network utilizing at least one variable resistor for responding to a wide dynamic range of load variations.
In accordance with a preferred embodiment of the invention, a variable amplitude voltage regulator (VAR) utilized in a power factor correction system operates as a resistor scaling network. The network consists of at least one variable resistor R2 (a JFET) and three fixed resistors R1, R3 and R4. A source of rectified alternating current input voltage (ACR) is coupled to the resistor scaling network. The output of a voltage error differential amplifier (VES) is coupled through a filter to the gate of the JFET (R2). The amplitude of the VES controls the resistance value of R2 such that the scaling network produces a demand level control signal (DLS) for the power factor correction circuit in accordance with the following formula:   DLS  =            (              R2                  R1          +          R2                    )        xc3x97          (              1        +                  R4          R3                    )        xc3x97    ACR  
wherein R2 varies as a function of the VES dc level.